Synchronizing circuit arrangements of the aforedefined kind are known to the art and are also standardized. For instance, it is known to provide in a multiplexing/demultiplexing unit a synchronizing circuit arrangement for synchronizing bit streams that are coordinated to form a data packet and to use the principle of dividing each data packet into an address-carrying section and an information-carrying section, and to divide the whole of the data packet into a given number of parts, one or more bytes or words. When practicing known techniques, a boundary can be established between two closely following data packets in a sequentially oriented bit stream divided into mutually sequential and clearly defined data packets, by constantly giving the bit positions a positional value within a predetermined defined part of a consecutive bit sequence of each transmitted data packet so that they will have a given value (for instance "0") predetermined by a predetermined check or control calculation.
A bit sequence belonging to a respective received data packet and corresponding to the aforesaid determined part of a consecutive bit sequence is evaluated in order to establish the extent to which said check calculation will give the predetermined value.
When agreement is found, the boundary between two mutually sequential data packets is established via the bit sequence of the selected part.
In the case of a multiplexing function, the bit stream coordinated within the data packet will occur on a number of incoming connections at a bit rate higher than 100 Mb/s and then at a higher rate on an outgoing connection, whereas the reverse applies in the case of a demultiplexing function, without changing the information content of the data packet.
With regard to the embodiment that describes the present invention, it can be mentioned that it is known to supplement a standardized ATM data cell or ATM data packet with an additional information-carrying bit position section which is intended to provide switch-internal address information and which is added to the standardized ATM data cell at the input to the switch unit and is removed at the output thereof.
An example of the earlier standpoint of technique in this regard is illustrated and described in U.S. Pat. No. 5,130,984.